Setting log file to 'D:/Lattice/Kurs13/impl1/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file 'D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs13/impl1/source/top.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs13/impl1/source/lcd_pwm.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs13/impl1/source/lcd.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs13/impl1/source/strobe_generator.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs13/impl1/source/decoder_7seg.v' INFO - D:/Lattice/Kurs13/impl1/source/top.v(4,8-4,11) (VERI-1018) compiling module 'top' INFO - D:/Lattice/Kurs13/impl1/source/top.v(4,1-93,10) (VERI-9000) elaborating module 'top' INFO - D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1' INFO - D:/Lattice/Kurs13/impl1/source/strobe_generator.v(3,1-35,10) (VERI-9000) elaborating module 'StrobeGenerator_uniq_1' INFO - D:/Lattice/Kurs13/impl1/source/decoder_7seg.v(4,1-42,10) (VERI-9000) elaborating module 'Decoder7seg_uniq_1' INFO - D:/Lattice/Kurs13/impl1/source/decoder_7seg.v(4,1-42,10) (VERI-9000) elaborating module 'Decoder7seg_uniq_2' INFO - D:/Lattice/Kurs13/impl1/source/decoder_7seg.v(4,1-42,10) (VERI-9000) elaborating module 'Decoder7seg_uniq_3' INFO - D:/Lattice/Kurs13/impl1/source/decoder_7seg.v(4,1-42,10) (VERI-9000) elaborating module 'Decoder7seg_uniq_4' INFO - D:/Lattice/Kurs13/impl1/source/lcd.v(4,1-233,10) (VERI-9000) elaborating module 'LCD_uniq_1' INFO - D:/Lattice/Kurs13/impl1/source/strobe_generator.v(3,1-35,10) (VERI-9000) elaborating module 'StrobeGenerator_uniq_2' INFO - D:/Lattice/Kurs13/impl1/source/lcd_pwm.v(4,1-32,10) (VERI-9000) elaborating module 'LCD_PWM_uniq_1' Done: design load finished with (0) errors, and (0) warnings