Place & Route TRACE Report
Loading design for application trce from file kurs13_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu May 18 15:31:14 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs13_impl1.twr -gui -msgset D:/Lattice/Kurs13/promote.xml Kurs13_impl1.ncd Kurs13_impl1.prf
Design file: kurs13_impl1.ncd
Preference file: kurs13_impl1.prf
Device,speed: LCMXO2-1200HC,5
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "Clock" 14.000112 MHz (0 errors) 962 items scored, 0 timing errors detected.
Report: 123.289MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "Clock" 14.000112 MHz ;
962 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i16 (to Clock +)
FF CountEnable_m/Counter_r_i15
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_2 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C15A.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C15A.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i4 (to Clock +)
FF CountEnable_m/Counter_r_i3
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_8 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_8:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C13C.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13C.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i12 (to Clock +)
FF CountEnable_m/Counter_r_i11
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_4 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C14C.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C14C.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i20 (to Clock +)
FF CountEnable_m/Counter_r_i19
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_0 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C15C.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C15C.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i0 (to Clock +)
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_10 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C13A.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13A.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i6 (to Clock +)
FF CountEnable_m/Counter_r_i5
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_7 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_7:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C13D.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13D.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i18 (to Clock +)
FF CountEnable_m/Counter_r_i17
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_1 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C15B.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C15B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i10 (to Clock +)
FF CountEnable_m/Counter_r_i9
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_5 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C14B.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C14B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i2 (to Clock +)
FF CountEnable_m/Counter_r_i1
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_9 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C13B.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 63.317ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i1 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i14 (to Clock +)
FF CountEnable_m/Counter_r_i13
Delay: 7.863ns (22.4% logic, 77.6% route), 4 logic levels.
Constraint Details:
7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_3 meets
71.428ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns
Physical Path Details:
Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C13B.CLK to R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE 2 1.813 R8C13B.Q0 to R9C18C.D1 CountEnable_m/Counter_r_1
CTOF_DEL --- 0.452 R9C18C.D1 to R9C18C.F1 SLICE_49
ROUTE 1 1.129 R9C18C.F1 to R8C15D.C1 CountEnable_m/n32
CTOF_DEL --- 0.452 R8C15D.C1 to R8C15D.F1 CountEnable_m/SLICE_61
ROUTE 1 1.018 R8C15D.F1 to R7C14A.C0 CountEnable_m/n35
CTOF_DEL --- 0.452 R7C14A.C0 to R7C14A.F0 CountEnable_m/SLICE_29
ROUTE 12 2.138 R7C14A.F0 to R8C14D.LSR CountEnable_m/Counter_r_20__N_79 (to Clock)
--------
7.863 (22.4% logic, 77.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C13B.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 34 3.173 OSC.OSC to R8C14D.CLK Clock
--------
3.173 (0.0% logic, 100.0% route), 0 logic levels.
Report: 123.289MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "Clock" 14.000112 MHz ; | 14.000 MHz| 123.289 MHz| 4
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock Source: OSCH_inst.OSC Loads: 34
Covered under: FREQUENCY NET "Clock" 14.000112 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 962 paths, 1 nets, and 527 connections (100.00% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu May 18 15:31:14 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs13_impl1.twr -gui -msgset D:/Lattice/Kurs13/promote.xml Kurs13_impl1.ncd Kurs13_impl1.prf
Design file: kurs13_impl1.ncd
Preference file: kurs13_impl1.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "Clock" 14.000112 MHz (0 errors) 962 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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Preference: FREQUENCY NET "Clock" 14.000112 MHz ;
962 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i13 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i13 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay CountEnable_m/SLICE_3 to CountEnable_m/SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path CountEnable_m/SLICE_3 to CountEnable_m/SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C14D.CLK to R8C14D.Q0 CountEnable_m/SLICE_3 (from Clock)
ROUTE 2 0.132 R8C14D.Q0 to R8C14D.A0 CountEnable_m/Counter_r_13
CTOF_DEL --- 0.101 R8C14D.A0 to R8C14D.F0 CountEnable_m/SLICE_3
ROUTE 1 0.000 R8C14D.F0 to R8C14D.DI0 CountEnable_m/Counter_r_20_N_58_13 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14D.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14D.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i16 (from Clock +)
Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i16 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_19 to LCD_inst/StrobeGenerator0/SLICE_19 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path LCD_inst/StrobeGenerator0/SLICE_19 to LCD_inst/StrobeGenerator0/SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C14A.CLK to R9C14A.Q1 LCD_inst/StrobeGenerator0/SLICE_19 (from Clock)
ROUTE 2 0.132 R9C14A.Q1 to R9C14A.A1 LCD_inst/StrobeGenerator0/Counter_r_16
CTOF_DEL --- 0.101 R9C14A.A1 to R9C14A.F1 LCD_inst/StrobeGenerator0/SLICE_19
ROUTE 1 0.000 R9C14A.F1 to R9C14A.DI1 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_16 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R9C14A.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R9C14A.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i10 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i10 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay CountEnable_m/SLICE_5 to CountEnable_m/SLICE_5 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path CountEnable_m/SLICE_5 to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C14B.CLK to R8C14B.Q1 CountEnable_m/SLICE_5 (from Clock)
ROUTE 2 0.132 R8C14B.Q1 to R8C14B.A1 CountEnable_m/Counter_r_10
CTOF_DEL --- 0.101 R8C14B.A1 to R8C14B.F1 CountEnable_m/SLICE_5
ROUTE 1 0.000 R8C14B.F1 to R8C14B.DI1 CountEnable_m/Counter_r_20_N_58_10 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14B.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14B.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i3 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i3 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay CountEnable_m/SLICE_8 to CountEnable_m/SLICE_8 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path CountEnable_m/SLICE_8 to CountEnable_m/SLICE_8:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C13C.CLK to R8C13C.Q0 CountEnable_m/SLICE_8 (from Clock)
ROUTE 2 0.132 R8C13C.Q0 to R8C13C.A0 CountEnable_m/Counter_r_3
CTOF_DEL --- 0.101 R8C13C.A0 to R8C13C.F0 CountEnable_m/SLICE_8
ROUTE 1 0.000 R8C13C.F0 to R8C13C.DI0 CountEnable_m/Counter_r_20_N_58_3 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C13C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C13C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i11 (from Clock +)
Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i11 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_21 to LCD_inst/StrobeGenerator0/SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path LCD_inst/StrobeGenerator0/SLICE_21 to LCD_inst/StrobeGenerator0/SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C13C.CLK to R9C13C.Q0 LCD_inst/StrobeGenerator0/SLICE_21 (from Clock)
ROUTE 2 0.132 R9C13C.Q0 to R9C13C.A0 LCD_inst/StrobeGenerator0/Counter_r_11
CTOF_DEL --- 0.101 R9C13C.A0 to R9C13C.F0 LCD_inst/StrobeGenerator0/SLICE_21
ROUTE 1 0.000 R9C13C.F0 to R9C13C.DI0 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_11 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R9C13C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R9C13C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i20 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i20 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay CountEnable_m/SLICE_0 to CountEnable_m/SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path CountEnable_m/SLICE_0 to CountEnable_m/SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C15C.CLK to R8C15C.Q1 CountEnable_m/SLICE_0 (from Clock)
ROUTE 2 0.132 R8C15C.Q1 to R8C15C.A1 CountEnable_m/Counter_r_20
CTOF_DEL --- 0.101 R8C15C.A1 to R8C15C.F1 CountEnable_m/SLICE_0
ROUTE 1 0.000 R8C15C.F1 to R8C15C.DI1 CountEnable_m/Counter_r_20_N_58_20 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C15C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C15C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i15 (from Clock +)
Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i15 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_19 to LCD_inst/StrobeGenerator0/SLICE_19 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path LCD_inst/StrobeGenerator0/SLICE_19 to LCD_inst/StrobeGenerator0/SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R9C14A.CLK to R9C14A.Q0 LCD_inst/StrobeGenerator0/SLICE_19 (from Clock)
ROUTE 2 0.132 R9C14A.Q0 to R9C14A.A0 LCD_inst/StrobeGenerator0/Counter_r_15
CTOF_DEL --- 0.101 R9C14A.A0 to R9C14A.F0 LCD_inst/StrobeGenerator0/SLICE_19
ROUTE 1 0.000 R9C14A.F0 to R9C14A.DI0 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_15 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R9C14A.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R9C14A.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i11 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i11 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay CountEnable_m/SLICE_4 to CountEnable_m/SLICE_4 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path CountEnable_m/SLICE_4 to CountEnable_m/SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C14C.CLK to R8C14C.Q0 CountEnable_m/SLICE_4 (from Clock)
ROUTE 2 0.132 R8C14C.Q0 to R8C14C.A0 CountEnable_m/Counter_r_11
CTOF_DEL --- 0.101 R8C14C.A0 to R8C14C.F0 CountEnable_m/SLICE_4
ROUTE 1 0.000 R8C14C.F0 to R8C14C.DI0 CountEnable_m/Counter_r_20_N_58_11 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14C.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i9 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i9 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay CountEnable_m/SLICE_5 to CountEnable_m/SLICE_5 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path CountEnable_m/SLICE_5 to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C14B.CLK to R8C14B.Q0 CountEnable_m/SLICE_5 (from Clock)
ROUTE 2 0.132 R8C14B.Q0 to R8C14B.A0 CountEnable_m/Counter_r_9
CTOF_DEL --- 0.101 R8C14B.A0 to R8C14B.F0 CountEnable_m/SLICE_5
ROUTE 1 0.000 R8C14B.F0 to R8C14B.DI0 CountEnable_m/Counter_r_20_N_58_9 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14B.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C14B.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CountEnable_m/Counter_r_i6 (from Clock +)
Destination: FF Data in CountEnable_m/Counter_r_i6 (to Clock +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay CountEnable_m/SLICE_7 to CountEnable_m/SLICE_7 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path CountEnable_m/SLICE_7 to CountEnable_m/SLICE_7:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C13D.CLK to R8C13D.Q1 CountEnable_m/SLICE_7 (from Clock)
ROUTE 2 0.132 R8C13D.Q1 to R8C13D.A1 CountEnable_m/Counter_r_6
CTOF_DEL --- 0.101 R8C13D.A1 to R8C13D.F1 CountEnable_m/SLICE_7
ROUTE 1 0.000 R8C13D.F1 to R8C13D.DI1 CountEnable_m/Counter_r_20_N_58_6 (to Clock)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to CountEnable_m/SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C13D.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to CountEnable_m/SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 34 1.216 OSC.OSC to R8C13D.CLK Clock
--------
1.216 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "Clock" 14.000112 MHz ; | 0.000 ns| 0.379 ns| 2
| | |
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All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock Source: OSCH_inst.OSC Loads: 34
Covered under: FREQUENCY NET "Clock" 14.000112 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 962 paths, 1 nets, and 527 connections (100.00% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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