Lattice Mapping Report File for Design Module 'top'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 5 -oc Commercial
     Kurs13_impl1.ngd -o Kurs13_impl1_map.ncd -pr Kurs13_impl1.prf -mp
     Kurs13_impl1.mrp -lpf D:/Lattice/Kurs13/impl1/Kurs13_impl1.lpf -lpf
     D:/Lattice/Kurs13/impl1/source/Kurs13.lpf -c 0 -gui -msgset
     D:/Lattice/Kurs13/promote.xml 
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200HCTQFP100
Target Performance:   5
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
Mapped on:  05/18/23  15:31:05


Design Summary
   Number of registers:     61 out of  1520 (4%)
      PFU registers:           61 out of  1280 (5%)
      PIO registers:            0 out of   240 (0%)
   Number of SLICEs:        69 out of   640 (11%)
      SLICEs as Logic/ROM:     69 out of   640 (11%)
      SLICEs as RAM:            0 out of   480 (0%)
      SLICEs as Carry:         29 out of   640 (5%)
   Number of LUT4s:        132 out of  1280 (10%)
      Number used as logic LUTs:         74
      Number used as distributed RAM:     0
      Number used as ripple logic:       58
      Number used as shift registers:     0
   Number of PIO sites used: 13 + 4(JTAG) out of 80 (21%)
   Number of block RAMs:  0 out of 7 (0%)
   Number of GSRs:        1 out of 1 (100%)
   EFB used :        No
   JTAG used :       No
   Readback used :   No
   Oscillator used : Yes
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  1
     Net Clock: 34 loads, 34 rising, 0 falling (Driver: OSCH_inst )
   Number of Clock Enables:  2
     Net CountEnable_w: 9 loads, 9 LSLICEs

     Net LCD_inst/ChangeState_w: 1 loads, 1 LSLICEs
   Number of LSRs:  2
     Net CountEnable_m/Counter_r_20__N_79: 11 loads, 11 LSLICEs
     Net LCD_inst/StrobeGenerator0/Counter_r_16__N_266: 9 loads, 9 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net LCD_inst/State_r_0: 21 loads
     Net LCD_inst/State_r_1: 16 loads
     Net Voltage_w_1: 14 loads
     Net LCD_inst/State_r_2: 13 loads
     Net Voltage_w_2: 13 loads
     Net CountEnable_m/Counter_r_20__N_79: 12 loads
     Net LCD_inst/StrobeGenerator0/Counter_r_16__N_266: 10 loads
     Net CountEnable_w: 9 loads
     Net Counter_r_10: 9 loads
     Net Counter_r_12: 9 loads




   Number of warnings:  1
   Number of errors:    0
     




Design Errors/Warnings

WARNING - map: OSCH 'OSCH_inst' has FREQUENCY preference value set to 14.00 MHZ,
     which is different from the actual value 14.00 MHZ. The FREQUENCY
     preference is still within the 5.5% tolerence of the actual value.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| ComPWM_o[2]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Reset               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SegPWM_o[0]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SegPWM_o[1]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SegPWM_o[2]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SegPWM_o[3]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SegPWM_o[4]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SegPWM_o[5]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SegPWM_o[6]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+

| SegPWM_o[7]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| ComPWM_o[0]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| ComPWM_o[1]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| ComPWM_o[3]         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Block i822 undriven or does not drive anything - clipped.
Signal LCD_inst/n965 was merged into signal LCD_inst/State_r_1
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal Counter_r_208_add_4_1/S0 undriven or does not drive anything - clipped.
Signal Counter_r_208_add_4_1/CI undriven or does not drive anything - clipped.
Signal LCD_inst/StrobeGenerator0/sub_6_add_2_1/S0 undriven or does not drive
     anything - clipped.
Signal LCD_inst/StrobeGenerator0/sub_6_add_2_1/CI undriven or does not drive
     anything - clipped.
Signal LCD_inst/StrobeGenerator0/sub_6_add_2_17/CO undriven or does not drive
     anything - clipped.
Signal Counter_r_208_add_4_17/S1 undriven or does not drive anything - clipped.
Signal Counter_r_208_add_4_17/CO undriven or does not drive anything - clipped.
Signal CountEnable_m/sub_6_add_2_1/S0 undriven or does not drive anything -
     clipped.
Signal CountEnable_m/sub_6_add_2_1/CI undriven or does not drive anything -
     clipped.
Signal CountEnable_m/sub_6_add_2_21/CO undriven or does not drive anything -
     clipped.
Block LCD_inst/i4_1_lut_rep_14 was optimized away.
Block i1 was optimized away.

     

OSC Summary
-----------

OSC 1:                                     Pin/Node Value
  OSC Instance Name:                                OSCH_inst
  OSC Type:                                         OSCH
  STDBY Input:                                      NONE
  OSC Output:                              NODE     Clock
  OSC Nominal Frequency (MHz):                      14.00



ASIC Components
---------------

Instance Name: OSCH_inst
         Type: OSCH







GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is 'Reset_c'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------

     These components have the GSR property set to ENABLED and the local reset
     is synchronous. The components will respond to the synchronous local reset
     and to the unrelated asynchronous reset signal 'Reset_c' via the GSR
     component.

     Type and number of components of the type: 
   Register = 38 

     Type and instance name of component: 
   Register : CountEnable_m/Counter_r_i0
   Register : CountEnable_m/Counter_r_i1
   Register : CountEnable_m/Counter_r_i20
   Register : CountEnable_m/Counter_r_i19
   Register : CountEnable_m/Counter_r_i18
   Register : CountEnable_m/Counter_r_i17
   Register : CountEnable_m/Counter_r_i16
   Register : CountEnable_m/Counter_r_i15
   Register : CountEnable_m/Counter_r_i14
   Register : CountEnable_m/Counter_r_i13
   Register : CountEnable_m/Counter_r_i12
   Register : CountEnable_m/Counter_r_i11
   Register : CountEnable_m/Counter_r_i10
   Register : CountEnable_m/Counter_r_i9
   Register : CountEnable_m/Counter_r_i8
   Register : CountEnable_m/Counter_r_i7
   Register : CountEnable_m/Counter_r_i6
   Register : CountEnable_m/Counter_r_i5
   Register : CountEnable_m/Counter_r_i4
   Register : CountEnable_m/Counter_r_i3
   Register : CountEnable_m/Counter_r_i2
   Register : LCD_inst/StrobeGenerator0/Counter_r_i16
   Register : LCD_inst/StrobeGenerator0/Counter_r_i15
   Register : LCD_inst/StrobeGenerator0/Counter_r_i14
   Register : LCD_inst/StrobeGenerator0/Counter_r_i13
   Register : LCD_inst/StrobeGenerator0/Counter_r_i12
   Register : LCD_inst/StrobeGenerator0/Counter_r_i11
   Register : LCD_inst/StrobeGenerator0/Counter_r_i10
   Register : LCD_inst/StrobeGenerator0/Counter_r_i9
   Register : LCD_inst/StrobeGenerator0/Counter_r_i8
   Register : LCD_inst/StrobeGenerator0/Counter_r_i7
   Register : LCD_inst/StrobeGenerator0/Counter_r_i6

   Register : LCD_inst/StrobeGenerator0/Counter_r_i5
   Register : LCD_inst/StrobeGenerator0/Counter_r_i4
   Register : LCD_inst/StrobeGenerator0/Counter_r_i3
   Register : LCD_inst/StrobeGenerator0/Counter_r_i2
   Register : LCD_inst/StrobeGenerator0/Counter_r_i0
   Register : LCD_inst/StrobeGenerator0/Counter_r_i1



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 40 MB
        













































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