Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Wed Apr 19 19:57:43 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock] 496 items scored, 126 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 0.992ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3JX CK \DUT/StrobeGenerator0/Counter_i16 (from Clock +) Destination: FD1S3AX D \DUT/StrobeGenerator0/Strobe_13 (to Clock +) Delay: 5.846ns (29.9% logic, 70.1% route), 4 logic levels. Constraint Details: 5.846ns data_path \DUT/StrobeGenerator0/Counter_i16 to \DUT/StrobeGenerator0/Strobe_13 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 0.992ns Path Details: \DUT/StrobeGenerator0/Counter_i16 to \DUT/StrobeGenerator0/Strobe_13 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DUT/StrobeGenerator0/Counter_i16 (from Clock) Route 2 e 1.002 \DUT/StrobeGenerator0/Counter[16] LUT4 --- 0.448 C to Z \DUT/StrobeGenerator0/i12_4_lut Route 1 e 0.788 \DUT/StrobeGenerator0/n29 LUT4 --- 0.448 A to Z \DUT/StrobeGenerator0/i708_4_lut Route 1 e 0.788 \DUT/StrobeGenerator0/n730 LUT4 --- 0.448 B to Z \DUT/StrobeGenerator0/i709_3_lut Route 18 e 1.521 \DUT/StrobeGenerator0/Counter_16__N_192 -------- 5.846 (29.9% logic, 70.1% route), 4 logic levels. Error: The following path violates requirements by 0.992ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3JX CK \DUT/StrobeGenerator0/Counter_i16 (from Clock +) Destination: FD1S3JX PD \DUT/StrobeGenerator0/Counter_i16 (to Clock +) Delay: 5.846ns (29.9% logic, 70.1% route), 4 logic levels. Constraint Details: 5.846ns data_path \DUT/StrobeGenerator0/Counter_i16 to \DUT/StrobeGenerator0/Counter_i16 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 0.992ns Path Details: \DUT/StrobeGenerator0/Counter_i16 to \DUT/StrobeGenerator0/Counter_i16 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DUT/StrobeGenerator0/Counter_i16 (from Clock) Route 2 e 1.002 \DUT/StrobeGenerator0/Counter[16] LUT4 --- 0.448 C to Z \DUT/StrobeGenerator0/i12_4_lut Route 1 e 0.788 \DUT/StrobeGenerator0/n29 LUT4 --- 0.448 A to Z \DUT/StrobeGenerator0/i708_4_lut Route 1 e 0.788 \DUT/StrobeGenerator0/n730 LUT4 --- 0.448 B to Z \DUT/StrobeGenerator0/i709_3_lut Route 18 e 1.521 \DUT/StrobeGenerator0/Counter_16__N_192 -------- 5.846 (29.9% logic, 70.1% route), 4 logic levels. Error: The following path violates requirements by 0.992ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3JX CK \DUT/StrobeGenerator0/Counter_i16 (from Clock +) Destination: FD1S3IX CD \DUT/StrobeGenerator0/Counter_i15 (to Clock +) Delay: 5.846ns (29.9% logic, 70.1% route), 4 logic levels. Constraint Details: 5.846ns data_path \DUT/StrobeGenerator0/Counter_i16 to \DUT/StrobeGenerator0/Counter_i15 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 0.992ns Path Details: \DUT/StrobeGenerator0/Counter_i16 to \DUT/StrobeGenerator0/Counter_i15 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DUT/StrobeGenerator0/Counter_i16 (from Clock) Route 2 e 1.002 \DUT/StrobeGenerator0/Counter[16] LUT4 --- 0.448 C to Z \DUT/StrobeGenerator0/i12_4_lut Route 1 e 0.788 \DUT/StrobeGenerator0/n29 LUT4 --- 0.448 A to Z \DUT/StrobeGenerator0/i708_4_lut Route 1 e 0.788 \DUT/StrobeGenerator0/n730 LUT4 --- 0.448 B to Z \DUT/StrobeGenerator0/i709_3_lut Route 18 e 1.521 \DUT/StrobeGenerator0/Counter_16__N_192 -------- 5.846 (29.9% logic, 70.1% route), 4 logic levels. Warning: 5.992 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock] | 5.000 ns| 5.992 ns| 4 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- \DUT/StrobeGenerator0/Counter_16__N_192 | 18| 126| 99.00% | | | \DUT/StrobeGenerator0/n730 | 1| 126| 99.00% | | | \DUT/StrobeGenerator0/n29 | 1| 72| 57.14% | | | \DUT/StrobeGenerator0/n26 | 1| 54| 42.86% | | | \DUT/StrobeGenerator0/Counter[3] | 2| 18| 14.29% | | | \DUT/StrobeGenerator0/Counter[4] | 2| 18| 14.29% | | | \DUT/StrobeGenerator0/Counter[8] | 2| 18| 14.29% | | | \DUT/StrobeGenerator0/Counter[11] | 2| 18| 14.29% | | | \DUT/StrobeGenerator0/Counter[12] | 2| 18| 14.29% | | | \DUT/StrobeGenerator0/Counter[15] | 2| 18| 14.29% | | | \DUT/StrobeGenerator0/Counter[16] | 2| 18| 14.29% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 126 Score: 124992 Constraints cover 496 paths, 65 nets, and 145 connections (43.7% coverage) Peak memory: 57552896 bytes, TRCE: 536576 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs