Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Thu May 18 15:31:04 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file: top_temp_lse.sdc 
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 71.428001 -waveform { 0.000000 35.714001 } -name Clock [ get_nets { Clock } ]
            955 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 65.426ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3JX    CK             \CountEnable_m/Counter_r_i0  (from Clock +)
   Destination:    FD1S3JX    PD             \CountEnable_m/Counter_r_i0  (to Clock +)

   Delay:                   5.856ns  (29.8% logic, 70.2% route), 4 logic levels.

 Constraint Details:

      5.856ns data_path \CountEnable_m/Counter_r_i0 to \CountEnable_m/Counter_r_i0 meets
     71.428ns delay constraint less
      0.146ns L_S requirement (totaling 71.282ns) by 65.426ns

 Path Details: \CountEnable_m/Counter_r_i0 to \CountEnable_m/Counter_r_i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \CountEnable_m/Counter_r_i0 (from Clock)
Route         2   e 1.002                                  \CountEnable_m/Counter_r[0]
LUT4        ---     0.448              B to Z              \CountEnable_m/i13_4_lut
Route         1   e 0.788                                  \CountEnable_m/n32
LUT4        ---     0.448              B to Z              \CountEnable_m/i16_4_lut
Route         1   e 0.788                                  \CountEnable_m/n35
LUT4        ---     0.448              A to Z              \CountEnable_m/i798_4_lut
Route        22   e 1.531                                  \CountEnable_m/Counter_r_20__N_79
                  --------
                    5.856  (29.8% logic, 70.2% route), 4 logic levels.


Passed:  The following path meets requirements by 65.426ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3JX    CK             \CountEnable_m/Counter_r_i0  (from Clock +)
   Destination:    FD1S3AX    D              \CountEnable_m/Strobe_o_13  (to Clock +)

   Delay:                   5.856ns  (29.8% logic, 70.2% route), 4 logic levels.

 Constraint Details:

      5.856ns data_path \CountEnable_m/Counter_r_i0 to \CountEnable_m/Strobe_o_13 meets
     71.428ns delay constraint less
      0.146ns L_S requirement (totaling 71.282ns) by 65.426ns

 Path Details: \CountEnable_m/Counter_r_i0 to \CountEnable_m/Strobe_o_13

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \CountEnable_m/Counter_r_i0 (from Clock)
Route         2   e 1.002                                  \CountEnable_m/Counter_r[0]
LUT4        ---     0.448              B to Z              \CountEnable_m/i13_4_lut
Route         1   e 0.788                                  \CountEnable_m/n32
LUT4        ---     0.448              B to Z              \CountEnable_m/i16_4_lut
Route         1   e 0.788                                  \CountEnable_m/n35
LUT4        ---     0.448              A to Z              \CountEnable_m/i798_4_lut
Route        22   e 1.531                                  \CountEnable_m/Counter_r_20__N_79
                  --------
                    5.856  (29.8% logic, 70.2% route), 4 logic levels.


Passed:  The following path meets requirements by 65.426ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3JX    CK             \CountEnable_m/Counter_r_i0  (from Clock +)
   Destination:    FD1S3JX    PD             \CountEnable_m/Counter_r_i1  (to Clock +)

   Delay:                   5.856ns  (29.8% logic, 70.2% route), 4 logic levels.

 Constraint Details:

      5.856ns data_path \CountEnable_m/Counter_r_i0 to \CountEnable_m/Counter_r_i1 meets
     71.428ns delay constraint less
      0.146ns L_S requirement (totaling 71.282ns) by 65.426ns

 Path Details: \CountEnable_m/Counter_r_i0 to \CountEnable_m/Counter_r_i1

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \CountEnable_m/Counter_r_i0 (from Clock)
Route         2   e 1.002                                  \CountEnable_m/Counter_r[0]
LUT4        ---     0.448              B to Z              \CountEnable_m/i13_4_lut
Route         1   e 0.788                                  \CountEnable_m/n32
LUT4        ---     0.448              B to Z              \CountEnable_m/i16_4_lut
Route         1   e 0.788                                  \CountEnable_m/n35
LUT4        ---     0.448              A to Z              \CountEnable_m/i798_4_lut
Route        22   e 1.531                                  \CountEnable_m/Counter_r_20__N_79
                  --------
                    5.856  (29.8% logic, 70.2% route), 4 logic levels.

Report: 6.002 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 71.428001          |             |             |
-waveform { 0.000000 35.714001 } -name  |             |             |
Clock [ get_nets { Clock } ]            |    71.428 ns|     6.002 ns|     4  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover  1341 paths, 164 nets, and 321 connections (47.7% coverage)


Peak memory: 58535936 bytes, TRCE: 73728 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs