-------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Wed May 17 21:47:56 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: top Device,speed: LCMXO2-1200HC,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 14.000112 MHz ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i0 (from Clock +) Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i0 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_27 to LCD_inst/StrobeGenerator0/SLICE_27 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path LCD_inst/StrobeGenerator0/SLICE_27 to LCD_inst/StrobeGenerator0/SLICE_27: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12A.CLK to R9C12A.Q1 LCD_inst/StrobeGenerator0/SLICE_27 (from Clock) ROUTE 2 0.132 R9C12A.Q1 to R9C12A.A1 LCD_inst/StrobeGenerator0/Counter_r_0 CTOF_DEL --- 0.101 R9C12A.A1 to R9C12A.F1 LCD_inst/StrobeGenerator0/SLICE_27 ROUTE 1 0.000 R9C12A.F1 to R9C12A.DI1 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_0 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_27: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_27: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i8 (from Clock +) Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i8 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_23 to LCD_inst/StrobeGenerator0/SLICE_23 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path LCD_inst/StrobeGenerator0/SLICE_23 to LCD_inst/StrobeGenerator0/SLICE_23: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C13A.CLK to R9C13A.Q1 LCD_inst/StrobeGenerator0/SLICE_23 (from Clock) ROUTE 2 0.132 R9C13A.Q1 to R9C13A.A1 LCD_inst/StrobeGenerator0/Counter_r_8 CTOF_DEL --- 0.101 R9C13A.A1 to R9C13A.F1 LCD_inst/StrobeGenerator0/SLICE_23 ROUTE 1 0.000 R9C13A.F1 to R9C13A.DI1 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_8 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C13A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C13A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i1 (from Clock +) Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i1 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_26 to LCD_inst/StrobeGenerator0/SLICE_26 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path LCD_inst/StrobeGenerator0/SLICE_26 to LCD_inst/StrobeGenerator0/SLICE_26: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12B.CLK to R9C12B.Q0 LCD_inst/StrobeGenerator0/SLICE_26 (from Clock) ROUTE 2 0.132 R9C12B.Q0 to R9C12B.A0 LCD_inst/StrobeGenerator0/Counter_r_1 CTOF_DEL --- 0.101 R9C12B.A0 to R9C12B.F0 LCD_inst/StrobeGenerator0/SLICE_26 ROUTE 1 0.000 R9C12B.F0 to R9C12B.DI0 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_1 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CountEnable_m/Counter_r_i15 (from Clock +) Destination: FF Data in CountEnable_m/Counter_r_i15 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay CountEnable_m/SLICE_2 to CountEnable_m/SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path CountEnable_m/SLICE_2 to CountEnable_m/SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C15A.CLK to R8C15A.Q0 CountEnable_m/SLICE_2 (from Clock) ROUTE 2 0.132 R8C15A.Q0 to R8C15A.A0 CountEnable_m/Counter_r_15 CTOF_DEL --- 0.101 R8C15A.A0 to R8C15A.F0 CountEnable_m/SLICE_2 ROUTE 1 0.000 R8C15A.F0 to R8C15A.DI0 CountEnable_m/Counter_r_20_N_58_15 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CountEnable_m/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C15A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CountEnable_m/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C15A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CountEnable_m/Counter_r_i0 (from Clock +) Destination: FF Data in CountEnable_m/Counter_r_i0 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay CountEnable_m/SLICE_10 to CountEnable_m/SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path CountEnable_m/SLICE_10 to CountEnable_m/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C13A.CLK to R8C13A.Q1 CountEnable_m/SLICE_10 (from Clock) ROUTE 2 0.132 R8C13A.Q1 to R8C13A.A1 CountEnable_m/Counter_r_0 CTOF_DEL --- 0.101 R8C13A.A1 to R8C13A.F1 CountEnable_m/SLICE_10 ROUTE 1 0.000 R8C13A.F1 to R8C13A.DI1 CountEnable_m/Counter_r_20_N_58_0 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CountEnable_m/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C13A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CountEnable_m/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C13A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CountEnable_m/Counter_r_i5 (from Clock +) Destination: FF Data in CountEnable_m/Counter_r_i5 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay CountEnable_m/SLICE_7 to CountEnable_m/SLICE_7 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path CountEnable_m/SLICE_7 to CountEnable_m/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C13D.CLK to R8C13D.Q0 CountEnable_m/SLICE_7 (from Clock) ROUTE 2 0.132 R8C13D.Q0 to R8C13D.A0 CountEnable_m/Counter_r_5 CTOF_DEL --- 0.101 R8C13D.A0 to R8C13D.F0 CountEnable_m/SLICE_7 ROUTE 1 0.000 R8C13D.F0 to R8C13D.DI0 CountEnable_m/Counter_r_20_N_58_5 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CountEnable_m/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C13D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CountEnable_m/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C13D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i5 (from Clock +) Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i5 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_24 to LCD_inst/StrobeGenerator0/SLICE_24 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path LCD_inst/StrobeGenerator0/SLICE_24 to LCD_inst/StrobeGenerator0/SLICE_24: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12D.CLK to R9C12D.Q0 LCD_inst/StrobeGenerator0/SLICE_24 (from Clock) ROUTE 2 0.132 R9C12D.Q0 to R9C12D.A0 LCD_inst/StrobeGenerator0/Counter_r_5 CTOF_DEL --- 0.101 R9C12D.A0 to R9C12D.F0 LCD_inst/StrobeGenerator0/SLICE_24 ROUTE 1 0.000 R9C12D.F0 to R9C12D.DI0 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_5 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CountEnable_m/Counter_r_i7 (from Clock +) Destination: FF Data in CountEnable_m/Counter_r_i7 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay CountEnable_m/SLICE_6 to CountEnable_m/SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path CountEnable_m/SLICE_6 to CountEnable_m/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C14A.CLK to R8C14A.Q0 CountEnable_m/SLICE_6 (from Clock) ROUTE 2 0.132 R8C14A.Q0 to R8C14A.A0 CountEnable_m/Counter_r_7 CTOF_DEL --- 0.101 R8C14A.A0 to R8C14A.F0 CountEnable_m/SLICE_6 ROUTE 1 0.000 R8C14A.F0 to R8C14A.DI0 CountEnable_m/Counter_r_20_N_58_7 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CountEnable_m/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C14A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CountEnable_m/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C14A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q LCD_inst/StrobeGenerator0/Counter_r_i2 (from Clock +) Destination: FF Data in LCD_inst/StrobeGenerator0/Counter_r_i2 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay LCD_inst/StrobeGenerator0/SLICE_26 to LCD_inst/StrobeGenerator0/SLICE_26 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path LCD_inst/StrobeGenerator0/SLICE_26 to LCD_inst/StrobeGenerator0/SLICE_26: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12B.CLK to R9C12B.Q1 LCD_inst/StrobeGenerator0/SLICE_26 (from Clock) ROUTE 2 0.132 R9C12B.Q1 to R9C12B.A1 LCD_inst/StrobeGenerator0/Counter_r_2 CTOF_DEL --- 0.101 R9C12B.A1 to R9C12B.F1 LCD_inst/StrobeGenerator0/SLICE_26 ROUTE 1 0.000 R9C12B.F1 to R9C12B.DI1 LCD_inst/StrobeGenerator0/Counter_r_16_N_249_2 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to LCD_inst/StrobeGenerator0/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R9C12B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CountEnable_m/Counter_r_i17 (from Clock +) Destination: FF Data in CountEnable_m/Counter_r_i17 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay CountEnable_m/SLICE_1 to CountEnable_m/SLICE_1 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path CountEnable_m/SLICE_1 to CountEnable_m/SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C15B.CLK to R8C15B.Q0 CountEnable_m/SLICE_1 (from Clock) ROUTE 2 0.132 R8C15B.Q0 to R8C15B.A0 CountEnable_m/Counter_r_17 CTOF_DEL --- 0.101 R8C15B.A0 to R8C15B.F0 CountEnable_m/SLICE_1 ROUTE 1 0.000 R8C15B.F0 to R8C15B.DI0 CountEnable_m/Counter_r_20_N_58_17 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CountEnable_m/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C15B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CountEnable_m/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 34 1.216 OSC.OSC to R8C15B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000112 MHz ; | 0.000 ns| 0.379 ns| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 34 Covered under: FREQUENCY NET "Clock" 14.000112 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 962 paths, 1 nets, and 527 connections (100.00% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0)