Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Thu May 18 15:31:03 2023 Command Line: synthesis -f Kurs13_impl1_lattice.synproj -gui -msgset D:/Lattice/Kurs13/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 5. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 5. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 5 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p D:/Lattice/Kurs13 (searchpath added) -p D:/Lattice/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p D:/Lattice/Kurs13/impl1 (searchpath added) -p D:/Lattice/Kurs13 (searchpath added) Verilog design file = D:/Lattice/Kurs13/impl1/source/top.v Verilog design file = D:/Lattice/Kurs13/impl1/source/lcd_pwm.v Verilog design file = D:/Lattice/Kurs13/impl1/source/lcd.v Verilog design file = D:/Lattice/Kurs13/impl1/source/strobe_generator.v Verilog design file = D:/Lattice/Kurs13/impl1/source/decoder_7seg.v NGD file = Kurs13_impl1.ngd -sdc option: SDC file input is D:/Lattice/Kurs13/impl1/source/timing.ldc. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file d:/lattice/kurs13/impl1/source/top.v. VERI-1482 Analyzing Verilog file d:/lattice/kurs13/impl1/source/lcd_pwm.v. VERI-1482 Analyzing Verilog file d:/lattice/kurs13/impl1/source/lcd.v. VERI-1482 Analyzing Verilog file d:/lattice/kurs13/impl1/source/strobe_generator.v. VERI-1482 Analyzing Verilog file d:/lattice/kurs13/impl1/source/decoder_7seg.v. VERI-1482 Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): top INFO - synthesis: d:/lattice/kurs13/impl1/source/top.v(4): compiling module top. VERI-1018 INFO - synthesis: D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH(NOM_FREQ="14.00"). VERI-1018 INFO - synthesis: d:/lattice/kurs13/impl1/source/strobe_generator.v(3): compiling module StrobeGenerator(CLOCK_HZ=14000000,PERIOD_US=100000). VERI-1018 INFO - synthesis: d:/lattice/kurs13/impl1/source/decoder_7seg.v(4): compiling module Decoder7seg. VERI-1018 INFO - synthesis: d:/lattice/kurs13/impl1/source/lcd.v(4): compiling module LCD(CLOCK_HZ=14000000,CHANGE_COM_US=5000). VERI-1018 INFO - synthesis: d:/lattice/kurs13/impl1/source/lcd_pwm.v(4): compiling module LCD_PWM. VERI-1018 INFO - synthesis: d:/lattice/kurs13/impl1/source/strobe_generator.v(3): compiling module StrobeGenerator(CLOCK_HZ=14000000,PERIOD_US=5000). VERI-1018 Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga. Package Status: Final Version 1.44. Top-level module name = top. INFO - synthesis: Extracted state machine for register '\LCD_inst/State_r' with sequential encoding State machine has 8 reachable states with original encodings of: 000 001 010 011 100 101 110 111 GSR instance connected to net Reset_c. Writing LPF file Kurs13_impl1.lpf. Results of NGD DRC are available in top_drc.log. Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file Kurs13_impl1.ngd. ################### Begin Area Report (top)###################### Number of register bits => 61 of 1520 (4 % ) CCU2D => 29 FD1P3AX => 18 FD1S3AX => 5 FD1S3IX => 15 FD1S3JX => 23 GSR => 1 IB => 1 L6MUX21 => 16 LUT4 => 91 OB => 12 OSCH => 1 PFUMX => 22 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : Clock, loads : 61 Clock Enable Nets Number of Clock Enables: 2 Top 2 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : CountEnable_m/Counter_r_20__N_79, loads : 22 Net : LCD_inst/State_r_0, loads : 21 Net : LCD_inst/StrobeGenerator0/Counter_r_16__N_266, loads : 18 Net : CountEnable_m/CountEnable_w, loads : 15 Net : Counter_r_14, loads : 13 Net : Counter_r_13, loads : 13 Net : Counter_r_12, loads : 13 Net : Counter_r_10, loads : 13 Net : Counter_r_9, loads : 13 Net : Counter_r_8, loads : 13 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 71.428001 | | | -waveform { 0.000000 35.714001 } -name | | | Clock [ get_nets { Clock } ] | 14.000 MHz| 166.611 MHz| 4 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 55.824 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.656 secs --------------------------------------------------------------