--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Wed May 17 21:47:56 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     top
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "Clock" 14.000112 MHz ;
            10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i0  (to Clock +)

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_10 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C13A.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13A.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i6  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i5

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_7 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C13D.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_7:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13D.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i10  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i9

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_5 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C14B.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C14B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i14  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i13

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_3 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C14D.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C14D.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i18  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i17

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_1 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_1:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C15B.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_1:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C15B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i8  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i7

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_6 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_6:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C14A.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_6:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C14A.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i4  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i3

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_8 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_8:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C13C.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_8:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13C.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i16  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i15

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_2 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_2:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C15A.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_2:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C15A.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i12  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i11

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_4 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C14C.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C14C.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 63.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              CountEnable_m/Counter_r_i1  (from Clock +)
   Destination:    FF         Data in        CountEnable_m/Counter_r_i20  (to Clock +)
                   FF                        CountEnable_m/Counter_r_i19

   Delay:               7.863ns  (22.4% logic, 77.6% route), 4 logic levels.

 Constraint Details:

      7.863ns physical path delay CountEnable_m/SLICE_9 to CountEnable_m/SLICE_0 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.248ns LSR_SET requirement (totaling 71.180ns) by 63.317ns

 Physical Path Details:

      Data path CountEnable_m/SLICE_9 to CountEnable_m/SLICE_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.409     R8C13B.CLK to      R8C13B.Q0 CountEnable_m/SLICE_9 (from Clock)
ROUTE         2     1.813      R8C13B.Q0 to R9C18C.D1      CountEnable_m/Counter_r_1
CTOF_DEL    ---     0.452      R9C18C.D1 to      R9C18C.F1 SLICE_49
ROUTE         1     1.129      R9C18C.F1 to R8C15D.C1      CountEnable_m/n32
CTOF_DEL    ---     0.452      R8C15D.C1 to      R8C15D.F1 CountEnable_m/SLICE_61
ROUTE         1     1.018      R8C15D.F1 to R7C14A.C0      CountEnable_m/n35
CTOF_DEL    ---     0.452      R7C14A.C0 to      R7C14A.F0 CountEnable_m/SLICE_29
ROUTE        12     2.138      R7C14A.F0 to R8C15C.LSR     CountEnable_m/Counter_r_20__N_79 (to Clock)
                  --------
                    7.863   (22.4% logic, 77.6% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to CountEnable_m/SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C13B.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to CountEnable_m/SLICE_0:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        34     3.173        OSC.OSC to R8C15C.CLK     Clock
                  --------
                    3.173   (0.0% logic, 100.0% route), 0 logic levels.

Report:  123.289MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "Clock" 14.000112 MHz ;   |   14.000 MHz|  123.289 MHz|   4  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: Clock   Source: OSCH_inst.OSC   Loads: 34
   Covered under: FREQUENCY NET "Clock" 14.000112 MHz ;


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 962 paths, 1 nets, and 527 connections (100.00% coverage)